Title:
|
FINITE STATE MACHINE-DATAPATH DESIGN, OPTIMIZATION, AND IMPLEMENTATION
|
By: |
Robert Reese, Justin Davis, Mitchell Thornton |
Format: |
Paperback |

List price:
|
£40.95 |
We currently do not stock this item, please contact the publisher directly for
further information.
|
|
|
|
|
ISBN 10: |
1598295292 |
ISBN 13: |
9781598295290 |
Publisher: |
MORGAN & CLAYPOOL PUBLISHERS |
Pub. date: |
1 December, 2007 |
Series: |
Synthesis Lectures on Digital Circuits and Systems |
Pages: |
113 |
Description: |
Explores the design space of combined FSM/Datapath implementations and examines performance issues in digital systems. This book presents design examples in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. |
Synopsis: |
Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required.This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL. |
Illustrations: |
1, black & white illustrations |
Publication: |
US |
Imprint: |
Morgan & Claypool Publishers |
Returns: |
Non-returnable |