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Item Details
Title: DESIGN AUTOMATION FOR TIMING-DRIVEN LAYOUT SYNTHESIS
By: Sachin S. Sapatnekar, Sung-Mo Kang
Format: Hardback

List price: £171.00


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ISBN 10: 0792392817
ISBN 13: 9780792392811
Publisher: SPRINGER
Pub. date: 31 October, 1992
Edition: 1993 ed.
Series: The Springer International Series in Engineering and Computer Science 198
Pages: 269
Description: The automation of layout synthesis design under stringent timing specifications is essential for VLSI circuits and systems design. Through a discussion of the essential design automation process steps and important models and algorithms, this book presents a unified systems approach that can be practiced for high-performance CMOS VLSI designs.
Synopsis: Moore's law [Noy77], which predicted that the number of devices in- tegrated on a chip would be doubled every two years, was accurate for a number of years. Only recently has the level of integration be- gun to slow down somewhat due to the physical limits of integration technology. Advances in silicon technology have allowed Ie design- ers to integrate more than a few million transistors on a chip; even a whole system of moderate complexity can now be implemented on a single chip. To keep pace with the increasing complexity in very large scale integrated (VLSI) circuits, the productivity of chip designers would have to increase at the same rate as the level of integration. Without such an increase in productivity, the design of complex systems might not be achievable within a reasonable time-frame. The rapidly increasing complexity of VLSI circuits has made de- 1 2 INTRODUCTION sign automation an absolute necessity, since the required increase in productivity can only be accomplished with the use of sophisticated design tools. Such tools also enable designers to perform trade-off analyses of different logic implementations and to make well-informed design decisions.
Illustrations: XXI, 269 p.
Publication: Netherlands
Imprint: Springer
Returns: Returnable
Some other items by this author:
CMOS DIGITAL INTEGRATED CIRCUITS (HB)
CMOS DIGITAL INTEGRATED CIRCUITS (HB)
CMOS DIGITAL INTEGRATED CIRCUITS (PB)
CMOS DIGITAL INTEGRATED CIRCUITS ANALYSIS & DESIGN (HB)
CMOS DIGITAL INTEGRATED CIRCUITS ANALYSIS & DESIGN (PB)
CMOS DIGITAL INTEGRATED CIRCUITS ANALYSIS & DESIGN (PB)
CMOS DIGITAL INTEGRATED CIRCUITS ANALYSIS & DESIGN (PB)
CMOS DIGITAL INTEGRATED CIRCUITS ANALYSIS AND DESIGN (HB)
CMOS DIGITAL INTEGRATED CIRCUITS ANALYSIS AND DESIGN (PB)
DESIGN AUTOMATION FOR TIMING-DRIVEN LAYOUT SYNTHESIS (PB)
DESIGNING DIGITAL COMPUTER SYSTEMS WITH VERILOG
DESIGNING DIGITAL COMPUTER SYSTEMS WITH VERILOG (HB)
DESIGNING DIGITAL COMPUTER SYSTEMS WITH VERILOG (PB)
ELECTROMIGRATION INSIDE LOGIC CELLS (HB)
ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS (HB)
HANDBOOK OF ALGORITHMS FOR PHYSICAL DESIGN AUTOMATION
HANDBOOK OF ALGORITHMS FOR PHYSICAL DESIGN AUTOMATION (HB)
HOT-CARRIER RELIABILITY OF MOS VLSI CIRCUITS (HB)
HOT-CARRIER RELIABILITY OF MOS VLSI CIRCUITS (PB)
LAYOUT OPTIMIZATION IN VLSI DESIGN (HB)
LAYOUT OPTIMIZATION IN VLSI DESIGN (PB)
MODELING OF ELECTRICAL OVERSTRESS IN INTEGRATED CIRCUITS (HB)
MODELING OF ELECTRICAL OVERSTRESS IN INTEGRATED CIRCUITS (PB)
PHYSICAL DESIGN FOR MULTICHIP MODULES (HB)
PHYSICAL DESIGN FOR MULTICHIP MODULES (PB)
ROUTING CONGESTION IN VLSI CIRCUITS (HB)
ROUTING CONGESTION IN VLSI CIRCUITS (PB)
THERMALLY-AWARE DESIGN (PB)
THREE-DIMENSIONAL INTEGRATED CIRCUIT DESIGN (HB)
THREE-DIMENSIONAL INTEGRATED CIRCUIT DESIGN (PB)
TIMING
TIMING (HB)
TIMING (PB)
TIMING ANALYSIS AND OPTIMIZATION OF SEQUENTIAL CIRCUITS (HB)

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