| Title:
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VERIFICATION METHODOLOGY MANUAL FOR SYSTEMVERILOG
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| By: |
Janick Bergeron, Eduard Cerny, Alan Hunter |
| Format: |
Paperback |
| List price:
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£109.99 |
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We currently do not stock this item, please contact the publisher directly for
further information.
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| ISBN 10: |
1461498139 |
| ISBN 13: |
9781461498131 |
| Publisher: |
BIRKHAUSER BOSTON INC |
| Pub. date: |
5 December, 2014 |
| Edition: |
2006 ed. |
| Pages: |
520 |
| Synopsis: |
Offers users the first resource guide that combines both the methodology and basics of SystemVerilog Addresses how all these pieces fit together and how they should be used to verify complex chips rapidly and thoroughly. Unique in its broad coverage of SystemVerilog, advanced functional verification, and the combination of the two. |
| Illustrations: |
biography |
| Publication: |
US |
| Imprint: |
Birkhauser Boston Inc |
| Returns: |
Returnable |